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Due to increased time-to-market constraints,§development of systems composed of new hardand§software becomes more and more challenging. Software§development needs to start at a time§when hardware is still under development and§therefore needs to be simulated on general purpose§workstations. If the hardware to be simulated is a§parallel system composed of both hard- and§software, powerful simulation tools are needed in§order to be useful for effective development.§With the Generic Simulation Framework, clock-cycle§accurate simulation for parallel devices§communicating with each other is possible. The tool§presented in this work is designed to support§different model techniques at various levels of§abstraction (even inside the same simulation run)§and is currently used for verification and§design-space exploration in the design process of a§parallel processor system. By adding hierarchical§levels reflecting the physical structure of the§simulation, and using certain synchronization§algorithms, a speedup is tried to be achieved.