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Logic Synthesis and SOC Prototyping

Name: Logic Synthesis and SOC Prototyping
Brand: Springer, Berlin
SKU: 24843032
Price: 95.12 EUR
Availability: InStock
Author: Vaibbhav Taraate
ISBN: 9789811513138

RTL Design using VHDL

Vaibbhav Taraate

Jezik

Angleščina

Knjiga Trda

Koda Libristo: 24843032

Založba Springer, Berlin, januar 2020

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers h... Celoten opis

Koda Libristo: 24843032

230 b

95.12 €

Na zalogi pri dobavitelju Odposlali bomo v 10-13 dneh

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This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.