Impoved Test Techniques for Network-on-Chip Based Memory Systems

The search for a cost effective interconnect architecture and increasing communication demand in Systems-on-Chip (SoC) designs have paved the route to Network-on-Chip (NoC) research a decade back. However, like all other designs, NoC based SoC designs must also be tested for defects. The research on different test techniques for NoC based systems suggest that focus has been primarily on finding improved test techniques for NoC based logic cores. However, the embedded memory content in NoC based systems have increased over the years and will continue to increase. Due to their high density, these embedded memories are more prone to defects than other type of on-chip circuits and therefore, require more importance when it comes to testing NoC based systems. This book covers the improvement brought about in the existing approaches of test of NoC based memory cores. The improvements have been considered along the along the following directions : test architecture, test scheduling algorithms and on-line test techniques. In addition, the book also covers novel test architectures which are based on concept of re-use of on-chip resources.