FIR Filter Using Adders Based On SPST Technique

Finite impulse response (FIR) filter is basic component used in Digital Signal Processing application. Multiplier is one of the key components used in (FIR) but due to large number of multiplication its hardware gets complex. Design of high speed, low power multipliers is carried out to decrease propagation time and power dissipation of a processing system.Choosing the exact technique and implementing it make a big difference in power dissipation. To enhance speed many changes have been made over the existing booth algorithm. Existing design of Spurious Power Suppression Technique (SPST) based multipliers has been modified to reduce power dissipation and increase speed. Unwanted switching activities can be removed by using this technique. To attain this there are two ways to design a pre-computation unit i.e. by using registers and by using AND gate. Design of SPST based multiplier has been implemented on Xilinx 14.7 using Verilog HDL. Experimental results show that a SPST based multiplier achieved ~45% speed improvement and ~35% of reduction in power dissipation. This proposed multiplier has been used in FIR filter to achieve great extent of reduction in power dissipation.